As described, the invention relates generally to the field of wafer fabrication and compositions formed therefrom.
While conventional fabrication methods for semiconductor substrates are two-dimensional, such structures have several disadvantages, including high power consumption (parasitic capacitance), long delay (via interconnection lengths), size and weight limitations, increased noise, and larger footprints. Fabrication in three-dimensions includes formation of vertical electrical interconnects. Current fabrication methods—of which there are two—rely on complicated and inefficient processes. The first method involves first bonding wafers vertically and then thinning said wafers followed by deep reactive ion etching (DRIE) of the wafers through the stack and finally deposition (plating) of an interconnect metal. The second method relies on formation of solder bumps as interconnects before bonding; typically interconnects are formed by a traditional flip-chip process. Stacked wafers are then filled by an underfill material (resin with fillers) to prevent thermal expansion and failure. The entire process, however, is only possible when interconnects are large (typically 50 microns or more in diameter and height).